Research Projects of MSLAB at UC Riverside

Project Name and Description	Funding Resources
Modeling, simulation and optimization of mixed-signal/RF/analog/Interconnect circuits. Due to exponential growth of VLSI circuit complexity and strong interested in Mixed-Signal/RF/Analog circuits due to booming wireless/wireline communication market, efficient simulation and design of those mixed-signal/RF/analog/interconnects become critical for System-on-a-Chip (SoC) design in the nanometer regime. Efficient compact modeling of those VLSI circuits is the key step toward IP-reuse SoC design paradigm. Specifically, our group investigates following topics: 1. Efficient Hierarchical Model Order Reduction (MOR) and Realization. 2. Terminal Reduction of Interconnect Circuits 3. MOR for multiple-terminal linear circuits 4. Nonlinear MOR based piece-wise linear method Publication (coming)	This project is sponsored by NSF CAREER Award(CCF-0448534), UC MICRO (#05-111, #06-252,#07-105),
High performance power/ground distribution and clock network optimization and analysis. Due to increasing power and reduced supply voltage, the voltage fluctuations in the on-chip power delivery networks become more pronounced as technology scales. Efficient simulation and optimization of power/ground networks and clock networks to verify and constraint the adverse signal integrity effects become imperative for physical design in nanometer regime. Specifically, our group looks at the following topics: 1. Fast scalable decoupling capacitor budgeting algorithms to reduce dynamic IR drop. 2. Fast P/G simulation methods. 3. Fast clock network simulation and optimization methods. 4. Package(C4) design and analysis methods. Publication (coming)	This project is sponsored by NSF (OISE-0451688) Cadence Design Systems Inc.(03-04,04-05), UC MICRO program (#04-088)) NFS (OISE-0623038).
Fast on-chip gate-level or architecture thermal analysis and dynamic thermal management Power density has become one of the major constraints on attaining processor performance as integrated circuits enter the realm of nanometer technology. On-chip temperature regulation becomes critical and must-have for package cost reduction and chip reliability improvement. Specifically we look at following topics: 1. Software-based solution for high accuracy on-chip thermal estimation (to replace on-chip error-prone physical thermal sensors) 2. Efficient control mechanisms to regulate on-chip temperature in high-performance microprocessors. 3. Fast gate/circuit level thermal analysis and thermal optimization at various physical level. Publication (coming)	This project is sponsored by NSF CCF- 0541456. and partially sponsored by UC Senate Research Funds (05-06).
Embedded system design based on FPGA platforms. We focus on the development of so-called Warp-processor, which can dynamically optimize their software to improve execution time and energy consumption. By performing optimizations at runtime, Warp processors have the advantages of eliminating tool flow restrictions and extra designer effort associated with traditional compile-time optimizations. We developed on-chip lean, yet fast FPGA router to dynamic implement the critical portion of the system into faster FPGA fabric (called Just-in-Time Compilation). 1. Riverside on-chip routing system (ROCR). 2. Warp tools. 3. Warp architecture. Publication (coming)	This project is leaded by Prof. F. Vahid in CSE department and is sponsored by SRC (No.2003-HJ-1046G)